There has arisen a problem that it takes a shorter time to write to each data signal line and each pixel, as a liquid crystal display device becomes more high-definition. For this reason, a method has been proposed in which a liquid crystal display panel is divided into an upper region and a lower region, and the upper and lower regions are driven by scan signal line drive circuits and data signal line drive circuits, respectively.
FIG. 4 illustrates an arrangement of a liquid crystal display device including such a liquid crystal display panel with divided upper and lower regions (see Patent Document 1, for example).
In FIG. 4, scan signal lines Y1 through Ym/2 of the upper half region of the display screen and a Dummy line are driven by an upper Y driver 105, and scan signal lines Ym/2+1 through Ym of the lower half region are driven by a lower Y driver 106. The upper Y driver 105 is provided with a clock signal CPVU and a start signal STVU, both of which are only for the upper Y driver, and the lower Y driver 106 is provided with a clock signal CPVD and a start signal STVD, both of which are only for the lower Y driver.
Data signal lines X1 through X2n are provided so as to intersect with the scan signal lines Y1 through Ym. The data signal lines are also separated into upper data signal lines X1U through X2nU, and lower data signal lines X1D through X2nD. The upper data signal lines are driven by an upper X driver 103, and the lower data signal lines are driven by a lower X driver 104. The upper X driver 103 is provided with upper image data DATXU, a clock signal CPXU, and a start signal STXU. The lower X driver 104 is provided with lower image data DATXD, a clock signal CPXD, and a start signal STXD.
At intersections of the scan signal lines Y1 through Ym/2 and the upper data signal lines X1U through X2nU, and of the scan signal lines Ym/2+1 through Ym and the lower data signal lines X1D through X2nD, TFTs 110 are provided, respectively, so that pixels are formed. When a scan signal line turns on a TFT 110, the TFT 110 connects a data signal line to a pixel electrode 112. This causes a voltage to be applied to a liquid crystal layer in accordance with display data. Further, each of the pixels includes a storage capacitor 111 formed with respect to the scan signal line, the scan signal line being adjacent to the pixel in an upper direction of the display screen.
Such an arrangement for driving a display panel that is divided into upper and lower regions is also disclosed in Patent Documents 2 and 3.
In a case of the display panel in which the divided upper and lower regions are driven independently, the data signal lines are separated into upper and lower data signal lines at a central part of the display panel in a step in which the TFT substrate is processed. A separating point where the data signal line is separated is usually around a region where the upper and lower regions are adjacent to each other, the region being around above the scan signal line or around above a storage capacitor line. For example, in FIG. 4, such a point is located around above the scan signal line Ym/2 or, as indicated by P, around above the scan signal line Ym/2+1.
The following description deals with a cross-sectional structure of the separating point P of the data signal line.
FIG. 5 is a plan view illustrating the vicinity of the separating point P. For convenience of explanation, the scan signal line is indicated by a reference numeral 11, and the data signal line is indicated by a reference numeral 12. A TFT 13 is provided at an intersection of a scan signal line 11 and a data signal line 12. The data signal line 12 is connected with a pixel electrode 14 via the TFT 13. In FIG. 5, the region above the pixel electrode 14 corresponds to the upper display screen, and the region below the pixel electrode 14 corresponds to the lower display screen. The separating point P of the data signal line 12 is provided so as to be closer to the upper display screen than a connection point between the data signal line 12 and a source electrode of the TFT 13. Further, in a case where a storage capacitor of the pixel is connected with a storage capacitor line, a storage capacitor line 30 is provided parallel to the scan signal line 11, as illustrated in a dashed two-doted line of FIG. 5.
FIG. 6 illustrates a cross-sectional structure of the TFT 13.
The TFT 13 has a general arrangement in which, on a glass substrate 21, a gate electrode 22, a gate insulating film 23, an i-layer (an intrinsic semiconductor layer) 24 of amorphous silicon (a semiconductor), an n+ layer 25 of microcrystal silicon (a semiconductor), a source electrode 26, a drain electrode 27, and a passivation film 28 are stacked in this order. The i-layer 24 is formed as a channel region, and the n+ layer 25 is formed as source and drain regions, and also as a contact layer for the source and drain electrodes. Further, the passivation film 28 includes, in a region adjacent to the TFT 13, a contact hole 29 via which the drain electrode 27 is connected with the pixel electrode 14.
The data signal line 12 is formed simultaneously with the manufacturing of the TFT 13 in a step of manufacturing the TFT substrate. This forming step is explained below with reference to process steps illustrated in FIG. 7
On the left side in FIG. 7, cross-sectional views taken along the line A-A′ of FIG. 5, that is, cross-sectional views of the TFT 13, are illustrated. On the right side in FIG. 7, cross-sectional views (taken along the line B-B′ of FIG. 5) of a region where the data signal line 12 is to be formed are illustrated.
In step 1, the gate electrode 22 of the TFT 13, and the scan signal line 11 are formed on the glass substrate 21. In step 2, the gate insulating film 23 is formed on the gate electrode 22 and the scan signal line 11. In step 3, the i-layer 24 and the n+ layer 25 are formed, in this order, on the gate insulating film 23. In step 4, by a photolithography process, the i-layer 24 and the n+ layer 25 are patterned (i) in a region where the TFT 13 should be provided, and (ii) in a predetermined region including a region above the scan signal line 11 in order to even a step in the vicinity of the scan signal line 11.
In step 5, the source electrode 26 and the drain electrode 27 of the TFT 13 are patterned. At this point, simultaneously with the forming of the source electrode 26, the data signal line 12 is formed adjacent to the source electrode 26. Further, of the data signal line 12, a point that is to be the separating point P for separating the data signal line 12 into the upper display screen side and the lower display screen side is arranged not to be stacked with a material of the data signal line 12. The point to be the separating point P is located on the i-layer 24 and the n+ layer 25 in the vicinity of and above the scan signal line 11, the point to be the separating point P being a relatively flat area where the i-layer 24 and the n+ layer 25 are not located directly above the scan signal line 11.
In step 6, the n+ layer 25 in the separating region, where the source electrode 26 and the drain electrode 27 are separated from each other in the TFT 13, is etched and removed. Further, the n+ layer 25 at the point to be the separating point P of the data signal line 12 is etched and removed. This causes the upper display screen side and the lower display screen side of the data signal line 12 to be electrically isolated at the separating point P. In step 7, the passivation film 28 is formed so as to cover the whole TFT 13 and the data signal line 12. Furthermore, in step 8, a transparent electrode ITO that is to function as the pixel electrode 14 is formed on the passivation film 28 of the TFT 13, and is connected with the drain electrode 27 via the contact hole 29 that is formed in advance by the photolithography process.
Note that as an alignment reference for the separating point P, the storage capacitor line 30 (see in FIG. 5) can be used instead of the scan signal line 11 (see FIGS. 5 and 7).    (Patent Document 1)    Japanese Unexamined Patent Publication No. 268261/1998 (Tokukaihei 10-268261, publication date: Oct. 9, 1998)    (Patent Document 2)    Japanese Unexamined Patent Publication No. 131635/2003 (Tokukai 2003-131635, publication date: May 9, 2003)    (Patent Document 3)    Japanese Unexamined Patent Publication No. 319342/1997 (Tokukaihei 9-319342, publication date: Dec. 12, 1997)